About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Design Technology Co-Optimization (DTCO) Engineer, you will bridge the gap between process technology and product architecture to define the next generation of data center-class silicon. You will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.
Responsibilities
Execute high-fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on data center-class IP.
Drive Design Technology Co-Optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails).
Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes.
Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what-if analysis of emerging transistor architectures.
Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in physical design (RTL-to-GDS) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools.
Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction.
Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in design technology co-optimization, including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation.
Experience with Register Transfer Level (RTL) synthesis and standard cell library optimization.
Expertise in power integrity and reliability analysis and physical verification.
Familiarity with IP blocks (e.g., high-performance CPU/GPU cores, SRAM arrays, or high-speed interconnects).