About the job
Define the joint optimization of model compression and silicon architecture for Amazon's next generation of edge and cloud inference accelerators. Your work will set the technical targets that propagate across the model, compiler, runtime, and silicon stack.
Responsibilities
• Define the hardware-aware compression roadmap for next-generation accelerators, working backward from accuracy targets on standard language and reasoning benchmarks including Massive Multitask Language Understanding (MMLU), GSM8K, HumanEval, and Instruction Following Evaluation (IFEval).
• Own the joint optimization of compression algorithms (post-training quantization, quantization-aware training, knowledge distillation, structured pruning) with the underlying hardware.
• Represent applied science in silicon architecture reviews and influence decisions across the memory and compute subsystems of the accelerator.
• Set the science roadmap for the compression techniques the next architecture must support; validate that compression algorithms achieve target accuracy on the benchmarks our products are evaluated against.
• Mentor a team of senior and mid-level applied scientists working on compression and hardware-aware training.
• Serve as a single-threaded technical leader for the codesign agenda, accountable to senior leadership review.
Qualifications
Minimum
- 3+ years of building machine learning models for business application experience
- PhD, or Master's degree and 6+ years of applied research experience
- Experience programming in Java, C++, Python or related language
- Experience with neural deep learning methods and machine learning
Preferred
- Experience with modeling tools such as R, scikit-learn, Spark MLLib, MxNet, Tensorflow, numpy, scipy etc.
- Experience with large scale distributed systems such as Hadoop, Spark etc.