About the job
Define the joint optimization of model compression and silicon architecture for Amazon's next generation of edge and cloud inference accelerators. Your work will set the technical targets that propagate across the model, compiler, runtime, and silicon stack.
Responsibilities
• Define the hardware-aware compression roadmap for next-generation accelerators, working backward from accuracy targets on standard language and reasoning benchmarks including Massive Multitask Language Understanding (MMLU), GSM8K, HumanEval, and Instruction Following Evaluation (IFEval).
• Own the joint optimization of compression algorithms (post-training quantization, quantization-aware training, knowledge distillation, structured pruning) with the underlying hardware.
• Represent applied science in silicon architecture reviews and influence decisions across the memory and compute subsystems of the accelerator.
• Set the science roadmap for the compression techniques the next architecture must support; validate that compression algorithms achieve target accuracy on the benchmarks our products are evaluated against.
• Mentor a team of senior and mid-level applied scientists working on compression and hardware-aware training.
• Serve as a single-threaded technical leader for the codesign agenda, accountable to senior leadership review.
Qualifications
Minimum
• Master's or PhD in Computer Science, Electrical Engineering, or a related field, or equivalent industry experience.
• Eight or more years of industry experience with a track record of first-author or senior-author publications at top-tier venues in machine learning systems, computer architecture, or efficient machine learning.
• Demonstrated experience defining or co-defining a hardware architecture that shipped, including silicon, Field Programmable Gate Array (FPGA), or large-scale software accelerator.
• Deep expertise in at least two of the following: low-bit quantization, structured and unstructured pruning, knowledge distillation, sparse computation, hardware-aware neural architecture search.
• Working knowledge of computer architecture fundamentals: memory hierarchy, dataflow architectures, on-chip interconnect.
Preferred
• Direct experience contributing to silicon architecture for machine learning inference.
• Published work demonstrating hardware-software codesign, where the compression algorithm and the hardware were optimized jointly rather than sequentially.
• Experience applying compression techniques at large-model scale (tens of billions of parameters).
• Familiarity with Application-Specific Integrated Circuit (ASIC) development flow, Register Transfer Level (RTL) review, or compiler intermediate representations including Multi-Level Intermediate Representation (MLIR) and OpenXLA.
• Experience with Mixture-of-Experts (MoE) inference architectures.
• Track record of mentoring senior applied scientists and shaping a multi-year research agenda.
• Prior experience with vertically integrated stacks where the same team owns model, compiler, runtime, and silicon.