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ChipStack AI

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Representative Papers

DUET: Agentic Design Understanding via Experimentation and Testing

Dec 05, 2025

Large language models (LLMs) exhibit limited capability in hardware design tasks—particularly RTL code understanding—due to their inability to infer dynamic timing behavior from static syntax alone, hindering performance in downstream applications such as code completion, documentation generation, and verification. To address this, we propose an AI agent framework grounded in a hypothesis-generation–experimental-validation闭环: LLMs formulate behavioral hypotheses about RTL modules, which are then rigorously tested via EDA toolchains—including simulation, waveform analysis, and formal verification—to iteratively refine the model’s internal representation. This approach transcends purely syntactic parsing, enabling deep semantic and temporal modeling of RTL designs. Experimental evaluation on formal verification tasks demonstrates that our method significantly outperforms baseline LLMs lacking experimental feedback, validating the effectiveness and necessity of dynamic, experiment-driven reasoning for enhancing hardware design understanding.

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Latest Papers

DUET: Agentic Design Understanding via Experimentation and Testing

Dec 05, 2025

Large language models (LLMs) exhibit limited capability in hardware design tasks—particularly RTL code understanding—due to their inability to infer dynamic timing behavior from static syntax alone, hindering performance in downstream applications such as code completion, documentation generation, and verification. To address this, we propose an AI agent framework grounded in a hypothesis-generation–experimental-validation闭环: LLMs formulate behavioral hypotheses about RTL modules, which are then rigorously tested via EDA toolchains—including simulation, waveform analysis, and formal verification—to iteratively refine the model’s internal representation. This approach transcends purely syntactic parsing, enabling deep semantic and temporal modeling of RTL designs. Experimental evaluation on formal verification tasks demonstrates that our method significantly outperforms baseline LLMs lacking experimental feedback, validating the effectiveness and necessity of dynamic, experiment-driven reasoning for enhancing hardware design understanding.

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