SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits
This work addresses the significant challenge posed by bias temperature instability (BTI) and random process–voltage (PV) variations to digital circuit reliability in deep-nanometer CMOS technologies, where conventional analysis methods suffer from high computational cost and poor scalability. To overcome these limitations, the paper proposes a novel gate-level delay distribution prediction framework that uniquely integrates random forest regression with Bayesian optimization. By leveraging offline training on Monte Carlo simulation data—bypassing time-consuming atomic parameter extraction—and employing Bayesian optimization for automated hyperparameter tuning, the approach achieves substantially improved accuracy and efficiency. Experimental validation on ISCAS85 benchmark circuits demonstrates a 94.54% reduction in analysis time compared to the state-of-the-art method, with an average prediction error of only 1.63%.