Institution profile

National Technical University of Athens

Academic institutioneurope · gr
Official website
Research library311linked papers
Opportunities0open roles
Selected work

Representative Papers

Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications

Oct 03, 2022IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip

To address the limitations of conventional processors—insufficient computational capability, radiation susceptibility, and lack of dynamic adaptability—in spaceborne AI/ML applications, this paper proposes a heterogeneous on-board acceleration architecture integrating radiation-hardened (rad-hard) and commercial-off-the-shelf (COTS) FPGAs with an AI-specific instruction-set processor (ASIP). The architecture innovatively combines rad-hard and COTS FPGA resources and incorporates custom compute units inspired by vision processing units (VPUs) and tensor processing units (TPUs), enabling deployment of high-order AI models and in-orbit dynamic reconfiguration. Through radiation-hardened design, a reconfigurable computing framework, and industrial-grade benchmarking, multi-platform prototype validation is achieved. Compared to representative spaceborne processors, the architecture delivers over 10× improvement in energy efficiency, enables real-time on-board image recognition and autonomous mission decision-making, and establishes a scalable architectural paradigm for high-reliability, high-performance spaceborne intelligent computing.

12 citationsRead paper

FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

Nov 28, 2021International Conference on Electronics, Circuits, and Systems

To address real-time processing challenges posed by high-computational algorithms and high-data-rate payloads in emerging space missions, this work proposes a heterogeneous co-processing architecture tailored for aerospace embedded systems. It pioneers deep integration of a Xilinx Kintex FPGA—responsible for frame synchronization, preprocessing, and hardware acceleration—with an Intel Myriad2 Vision Processing Unit (VPU) dedicated to AI/DSP-intensive computations, interconnected via a low-overhead CIF/LCD parallel interface. The design includes a customized DSP/AI benchmark suite and a joint resource–power optimization strategy. Experimental results demonstrate a VPU AI throughput of 1.2 TOPS (INT8), FPGA resource utilization below 45%, 37% reduction in end-to-end latency, and total system power consumption ≤8.3 W. This work establishes a scalable, low-power, energy-efficient heterogeneous computing paradigm for on-board real-time intelligent processing.

11 citationsRead paper

Terminal-Bench: Benchmarking Agents on Hard, Realistic Tasks in Command Line Interfaces

Jan 17, 2026

This work addresses the challenge that existing AI agent benchmarks inadequately evaluate performance on real-world, complex, and long-horizon command-line tasks. To bridge this gap, the authors introduce a novel evaluation benchmark comprising 89 high-difficulty terminal tasks, all derived from authentic workflows and accompanied by isolated execution environments, human-authored reference solutions, and automated verification tests. The benchmark is designed to ensure realism, verifiability, and diversity, substantially narrowing the disparity between practical scenarios and current model evaluation paradigms. Experimental results demonstrate that even state-of-the-art agents achieve success rates below 65% on this benchmark. The paper further provides comprehensive error analysis and publicly releases the dataset and evaluation toolchain to support future research in this domain.

9 citations1 influentialRead paper

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space

Oct 03, 2022IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip

To address the demand for high-throughput, low-latency, and highly reliable on-board intelligent real-time processing under space radiation, this work tackles task interruption caused by single-event upsets (SEUs) in commercial heterogeneous accelerators—specifically Zynq FPGAs and Myriad VPUs. We propose an end-to-end collaborative fault-tolerant architecture. Our method integrates multi-level heterogeneous redundancy: on the FPGA side, dynamic memory scrubbing, partial reconfiguration, and triple modular redundancy (TMR); on the VPU side, SHAVE-core-level redundancy, ECC-protected instruction/data memories, and a custom CRC-enhanced CIF/LCD interface. A collaborative watchdog mechanism and extended communication protocols ensure cross-chip consistency. Evaluated on real on-board platforms—including CogniSat and Q7S—the architecture significantly reduces SEU-induced task interruptions, enabling robust, efficient, and radiation-hardened on-board intelligent processing.

3 citationsRead paper

Carbon Footprint Evaluation of Code Generation through LLM as a Service

Mar 30, 2025

As AI code generation is increasingly deployed in high-reliability domains such as automotive systems, quantifying its embodied carbon (from development) and operational carbon (from execution) has become critically urgent. Method: This paper introduces the first code-level, full-lifecycle carbon footprint assessment framework tailored for LLM-based coding services—exemplified by GitHub Copilot—integrating hardware-aware and software-aware carbon modeling with established software sustainability metrics to yield a reproducible empirical evaluation pipeline. Contribution/Results: We demonstrate that carbon impact varies significantly across usage scenarios; moreover, green coding strategies substantially reduce functional carbon intensity (e.g., gCO₂e per feature or per executed line). This work delivers the first measurable, verifiable carbon assessment methodology for AI-generated code in safety-critical domains, enabling evidence-based green AI development practices and informing sustainable AI policy formulation.

1 citationsRead paper
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