DSLR-CNN: Efficient CNN Acceleration Using Digit-Serial Left-to-Right Arithmetic
To address energy-efficiency and latency bottlenecks in CNN hardware acceleration, this paper proposes DSLRCNN, a domain-specific accelerator leveraging left-to-right (LR) digit-serial arithmetic. It innovatively integrates LR digit-serial computation—operating in most-significant-digit-first (MSDF) mode—into CNN accelerator design, enabling fine-grained digit-level pipelining and parallel multiply-accumulate (MAC) operations under low interconnect overhead and small area constraints. Implemented in Verilog and synthesized in GSCL 45nm CMOS technology, DSLRCNN incorporates custom LR multipliers/adders and a digit-level pipelined convolution engine. Evaluated on AlexNet, VGG-16, and ResNet-18, it achieves 4.37×–569.11× higher peak throughput and 3.58×–44.75× improved energy efficiency (TOPS/W) over baseline accelerators, while significantly reducing inference latency, silicon area, and power consumption.