Selected work

Representative Papers

HE^2: A Communication-Light Heterogeneous Architecture for Efficient Fully Homomorphic Encryption

May 29, 2026

This work addresses the significant computational and memory overheads of CKKS fully homomorphic encryption, which have limited existing ASIC or near-memory acceleration approaches due to high hardware costs, low efficiency, and severe heterogeneous communication latency. To overcome these challenges, the authors propose HE², a communication-light xPU-xMU heterogeneous acceleration architecture that, for the first time, systematically optimizes ModUp and ModDown operations at the dataflow graph (DFG) level. HE² integrates parallel keyswitch blocks to substantially reduce communication frequency and introduces a group-level pipelined execution mechanism that effectively exploits inter-group parallelism to hide communication latency. Compared to the state-of-the-art accelerator, HE² achieves a 1.66× end-to-end performance improvement, a 9.23× reduction in energy-delay-area product (EDAP), and limits communication stalls to only 6.67% of total execution latency.

0 citationsRead paper

PrimitiveVLA: Learning Reusable Motion Primitives for Efficient and Generalizable Robotic Manipulation

May 27, 2026

Existing vision-language-action (VLA) models suffer from low data efficiency and limited generalization due to their direct mapping of instructions to control signals. This work proposes PrimitiveVLA, a novel action-centric “decompose-and-compose” framework that first extracts reusable motion primitives through automated trajectory decomposition. It introduces a Multimodal Canonical Representation (MCR) to unify primitive learning and composition within a shared embedding space. Execution is realized via a closed-loop architecture integrating a vision-language model (VLM) planner with a switching module guided by large language model (LLM)-generated high-level plans. This approach substantially improves data efficiency and demonstrates exceptional zero-shot generalization on both unseen tasks and long-horizon sequential tasks.

0 citationsRead paper

QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

Mar 15, 2026

Existing general-purpose large language models exhibit limited performance on the natural language to SystemVerilog assertion (NL2SVA) task, primarily due to the scarcity of high-quality real-world SVA corpora and the absence of reliable methods for assessing semantic equivalence between natural language specifications and SVA code. To address this, this work proposes an RTL-guided bidirectional data synthesis framework that leverages open-source RTL designs to generate large-scale NL↔SVA translation pairs, followed by semantic consistency filtering to construct high-quality training data. Using this approach, we train CodeV-SVA, the first family of specialized large models for NL2SVA. The CodeV-SVA-14B variant achieves 75.8% and 84.0% Func.@1 accuracy on the NL2SVA-Human and NL2SVA-Machine benchmarks, respectively, matching or surpassing the performance of state-of-the-art models such as GPT-5 and DeepSeek-R1.

0 citationsRead paper

Hardwired-Neurons Language Processing Units as General-Purpose Cognitive Substrates

Aug 22, 2025

To address the dual bottlenecks of high energy consumption in large language model (LLM) inference and prohibitively expensive mask costs for application-specific integrated circuits (e.g., photomask set fabrication), this work proposes the Hardwired Neuron Language Processing Unit (HNLPU) architecture. Its core innovation is Metal-Embedding—a technique that physically embeds LLM weights directly into the 3D metal interconnect topology of a 5 nm process, achieving hardware-level weight fixation. This approach improves weight storage density by 15× and reduces non-recurring engineering (NRE) mask costs by 112×, significantly alleviating NRE economic constraints. The chip employs standardized photolithographic masks, ensuring both high integration density and manufacturability. Experimental evaluation demonstrates a throughput of 249,960 tokens/s and an energy efficiency of 36 tokens/J—over 1,000× higher than state-of-the-art GPUs—while reducing carbon footprint by 230× and improving overall cost-effectiveness by 8.57×.

0 citationsRead paper

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Jul 21, 2025

Existing Verilog generation benchmarks are overly simplified and fail to capture the complexity of real-world IP-level hardware design—such as ambiguous specifications and lax verification practices. Method: We introduce VeraBench, the first benchmark targeting realistic hardware design workflows. It comprises 12 open-source IP cores, multimodal specifications (textual descriptions, waveform diagrams, and interface definitions), and a rigorous verification environment requiring 100% line-coverage simulation plus formal verification. VeraBench supports dual-granularity evaluation at both module and system levels. Contribution/Results: Experiments reveal fundamental limitations of current LLMs in end-to-end hardware generation: the state-of-the-art model o1-preview achieves only 13.3% pass@1 on module-level tasks and fails all system-level tasks. VeraBench establishes a reproducible, scalable, and industrially relevant evaluation standard for LLM-driven hardware design, providing concrete directions for future improvement.

0 citationsRead paper

Recent publications

Latest Papers

HE^2: A Communication-Light Heterogeneous Architecture for Efficient Fully Homomorphic Encryption

May 29, 2026

This work addresses the significant computational and memory overheads of CKKS fully homomorphic encryption, which have limited existing ASIC or near-memory acceleration approaches due to high hardware costs, low efficiency, and severe heterogeneous communication latency. To overcome these challenges, the authors propose HE², a communication-light xPU-xMU heterogeneous acceleration architecture that, for the first time, systematically optimizes ModUp and ModDown operations at the dataflow graph (DFG) level. HE² integrates parallel keyswitch blocks to substantially reduce communication frequency and introduces a group-level pipelined execution mechanism that effectively exploits inter-group parallelism to hide communication latency. Compared to the state-of-the-art accelerator, HE² achieves a 1.66× end-to-end performance improvement, a 9.23× reduction in energy-delay-area product (EDAP), and limits communication stalls to only 6.67% of total execution latency.

0 citationsRead paper

PrimitiveVLA: Learning Reusable Motion Primitives for Efficient and Generalizable Robotic Manipulation

May 27, 2026

Existing vision-language-action (VLA) models suffer from low data efficiency and limited generalization due to their direct mapping of instructions to control signals. This work proposes PrimitiveVLA, a novel action-centric “decompose-and-compose” framework that first extracts reusable motion primitives through automated trajectory decomposition. It introduces a Multimodal Canonical Representation (MCR) to unify primitive learning and composition within a shared embedding space. Execution is realized via a closed-loop architecture integrating a vision-language model (VLM) planner with a switching module guided by large language model (LLM)-generated high-level plans. This approach substantially improves data efficiency and demonstrates exceptional zero-shot generalization on both unseen tasks and long-horizon sequential tasks.

0 citationsRead paper

QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

Mar 15, 2026

Existing general-purpose large language models exhibit limited performance on the natural language to SystemVerilog assertion (NL2SVA) task, primarily due to the scarcity of high-quality real-world SVA corpora and the absence of reliable methods for assessing semantic equivalence between natural language specifications and SVA code. To address this, this work proposes an RTL-guided bidirectional data synthesis framework that leverages open-source RTL designs to generate large-scale NL↔SVA translation pairs, followed by semantic consistency filtering to construct high-quality training data. Using this approach, we train CodeV-SVA, the first family of specialized large models for NL2SVA. The CodeV-SVA-14B variant achieves 75.8% and 84.0% Func.@1 accuracy on the NL2SVA-Human and NL2SVA-Machine benchmarks, respectively, matching or surpassing the performance of state-of-the-art models such as GPT-5 and DeepSeek-R1.

0 citationsRead paper

Hardwired-Neurons Language Processing Units as General-Purpose Cognitive Substrates

Aug 22, 2025

To address the dual bottlenecks of high energy consumption in large language model (LLM) inference and prohibitively expensive mask costs for application-specific integrated circuits (e.g., photomask set fabrication), this work proposes the Hardwired Neuron Language Processing Unit (HNLPU) architecture. Its core innovation is Metal-Embedding—a technique that physically embeds LLM weights directly into the 3D metal interconnect topology of a 5 nm process, achieving hardware-level weight fixation. This approach improves weight storage density by 15× and reduces non-recurring engineering (NRE) mask costs by 112×, significantly alleviating NRE economic constraints. The chip employs standardized photolithographic masks, ensuring both high integration density and manufacturability. Experimental evaluation demonstrates a throughput of 249,960 tokens/s and an energy efficiency of 36 tokens/J—over 1,000× higher than state-of-the-art GPUs—while reducing carbon footprint by 230× and improving overall cost-effectiveness by 8.57×.

0 citationsRead paper

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Jul 21, 2025

Existing Verilog generation benchmarks are overly simplified and fail to capture the complexity of real-world IP-level hardware design—such as ambiguous specifications and lax verification practices. Method: We introduce VeraBench, the first benchmark targeting realistic hardware design workflows. It comprises 12 open-source IP cores, multimodal specifications (textual descriptions, waveform diagrams, and interface definitions), and a rigorous verification environment requiring 100% line-coverage simulation plus formal verification. VeraBench supports dual-granularity evaluation at both module and system levels. Contribution/Results: Experiments reveal fundamental limitations of current LLMs in end-to-end hardware generation: the state-of-the-art model o1-preview achieves only 13.3% pass@1 on module-level tasks and fails all system-level tasks. VeraBench establishes a reproducible, scalable, and industrially relevant evaluation standard for LLM-driven hardware design, providing concrete directions for future improvement.

0 citationsRead paper